2026-07-03 
Views: 113 “The test of a first-rate intelligence is the ability to hold two opposed ideas in mind at the same time and still retain the ability to function.”
— F. Scott Fitzgerald, “The Crack-Up”
In 1936, Fitzgerald was at a low point in his life. On one hand, he was a symbol of the Jazz Age and a free-spending social icon; on the other, he aspired to be a serious, disciplined literary master in pursuit of immortality. Those two identities pulled against each other and could not be reconciled in reality, eventually leading to a “crack-up.”
GPU architects face a similarly stark choice. Immediate-Mode Rendering (IMR) uses the most direct pipeline to minimize draw latency. Tile-Based Rendering (TBR), by contrast, reorganizes the pipeline around tiles in an effort to eliminate much of the power consumed by data movement.
Mobile devices are battery-powered, so every milliwatt matters. Across the total energy required to render a frame, moving data between the chip and main memory consumes far more energy than computation itself. TBR therefore reorganizes geometry by tile, keeps the most expensive depth and color data on-chip, and transfers data to main memory only once when a tile is complete. What TBR saves is not computation, but data movement.
To make an informed choice between the two architectures, the first question is therefore quantitative: how much bandwidth can actually be saved?
Bandwidth
The communication between a GPU and main memory during one rendered frame can be divided into three components:
𝐵𝑊 = 𝐵𝑊Geo + 𝐵𝑊Depth + 𝐵𝑊Color
- Geometry cost, 𝐵𝑊Geo: temporary storage and retrieval of vertex attributes and triangle indices.
- Depth cost, 𝐵𝑊Depth: reads and writes of the depth buffer.
- Color cost, 𝐵𝑊Color: writes to the color buffer, plus additional transfers caused by render-pass transitions.
The following sections decompose these costs from the IMR and TBR perspectives.
IMR is simple and direct: both the depth buffer and color buffer reside in main memory, and each draw interacts with main memory directly. For every pixel drawn—whether or not the pixel is ultimately visible—the pipeline performs three operations: read depth, write depth, and write color.
Modern GPUs, however, include on-chip caches. If the requested data is already in cache, there is no need to access main memory. Let H denote the cache hit rate; the proportion that reaches main memory is therefore 1 − H.
This yields the three IMR cost components: 𝐵𝑊Geo = 0 𝐵𝑊Depth = P × R × S × O × 2Bd × (1 − H) 𝐵𝑊Color = P × R × S × O × Bc × (1 − H) Summing the three terms yields the total IMR bandwidth: 𝐵𝑊IMR = P × R × S × O × [(2Bd + Bc) × (1 − H)] |
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Key point. The first term, 𝐵𝑊Geo, is zero. IMR processes geometry as a stream: once vertex data has passed through the shader, the output proceeds directly to rasterization, with no need to stage geometry in main memory. This “zero” becomes a decisive factor later in the analysis. | |
TBR takes a fundamentally different approach. The screen is divided into tiles. Depth testing and color blending for each tile are completed entirely in on-chip storage, without any interaction with main memory. Only after the tile is finished is the final color written back once to main memory.
The price of this approach is geometry staging. Before each pass begins, TBR must write geometry data into a temporary region in main memory, then read it back during tile-by-tile rasterization. The write-read round trip produces 2G of traffic per pass, where G is the geometry complexity factor: the total volume of vertex-related data in one frame, measured in bytes. Pass transitions add another cost. A flush forces multisampled color data to be written out, and a restore reads that data back. One round trip between passes therefore transfers BC × 2S bytes per pixel.
This yields the three TBR cost components: 𝐵𝑊Geo = 2 × P × G 𝐵𝑊Depth = 0 𝐵𝑊Color = R × BC × [1 + 2S × (P − 1)] Summing the three terms yields the total TBR bandwidth: 𝐵𝑊TBR = 2 × P × G + R × BC × [1 + 2S × (P − 1)] |
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Placing the two bandwidth structures side by side makes the trade-off clear:
| Cost type | IMR | TBR |
|---|---|---|
| Geometry, 𝐵𝑊Geo | 0 | 2PG |
| Depth, 𝐵𝑊Depth | 2PRSOBd(1 − H) | 0 |
| Color, 𝐵𝑊Color | PRSOBc(1 − H) | RBC[1 + 2S(P − 1)] |
| Total bandwidth | PRSO[(2Bd + Bc)(1 − H)] | 2PG + RBC[1 + 2S(P − 1)] |
IMR wins on zero geometry cost; TBR wins on zero depth cost. The strengths and weaknesses of the two architectures are complementary.
Discriminant
To focus the discussion on the factors that truly vary, several parameters are fixed using practical assumptions:
| Parameter | Fixed value | Rationale |
|---|---|---|
| S | 1 | MSAA has been widely replaced in modern pipelines by techniques such as TAA and DLSS. |
| O | 2 | Front-to-back rendering and Early-Z can reduce overdraw but cannot eliminate it. Bounding-box-based object sorting cannot guarantee pixel-level depth order, and interleaved occlusion inevitably introduces redundant drawing. Real overdraw for opaque objects is commonly in the 1.5–2.5 range. |
| Bd | 4 | Common D24S8 format: 3 bytes for depth plus 1 byte for stencil. |
| Bc | 4 | Common RGBA8 format: four channels at 1 byte per channel. |
After substitution, the two formulas simplify substantially:
𝐵𝑊IMR = 24PR(1 − H)
𝐵𝑊TBR = 2PG + 4R(2P − 1)
Discriminant Δ
TBR is preferred when 𝐵𝑊TBR < 𝐵𝑊IMR. Substituting the simplified formulas, moving terms, and rearranging yields:
Δ = G − 2R(4 − 6H + 1P)
The decision rule is then:
| Case | Conclusion |
|---|---|
| Δ < 0 | TBR uses less bandwidth |
| Δ > 0 | IMR uses less bandwidth |
| Δ = 0 | Bandwidth is equal |
How Each Factor Moves the Decision Boundary
A single table does not reveal the full mechanism. The following points show how each factor shifts the decision boundary.
Resolution R: Tile-based rendering is nearly immune to the complexity represented by R. As resolution rises, the subtracted term becomes larger and Δ becomes smaller. IMR’s pixel cost scales with resolution, while TBR’s geometry cost remains unchanged.
Cache hit rate H: The cache hit rate is IMR’s shield. Every 0.1 increase in H reduces IMR’s main-memory traffic by 10%. TBR’s geometry-staging cost receives no protection from cache: its tile storage does not require cache, but it also cannot benefit from cache. When H is high enough to make the threshold (2R(4 − 6H + 1/P)) negative, the criterion points unconditionally to IMR. A large cache can therefore change the sign of the formula itself.
Number of passes P: The number of passes is TBR’s hidden tax. Each additional pass adds another geometry round trip and another transition transfer for TBR. For IMR, one additional pass adds only another round of pixel cost. The more fragmented the rendering pipeline becomes, the heavier TBR’s accumulated overhead.
Geometry volume G: Geometry volume is TBR’s most sensitive pressure point. As G increases, Δ increases. Modern geometry amplification techniques, including tessellation and mesh shaders, can multiply vertex volume inside the GPU. For IMR, that expanded data only passes briefly through a streaming pipeline. For TBR, the staging buffer must absorb the rapidly growing intermediate data. Every increase in geometry volume adds directly to TBR’s burden.
The following two examples show how Δ decides in representative scenarios.
Under the public-data assumptions and custom metric definitions used in this article, the following examples illustrate only how to apply the discriminant. The parameters are simplified assumptions and do not represent measured performance for any specific game, device, or GPU. No single causal conclusion is asserted.
Case A: Mobile Game with Forward Rendering
This case represents a mobile open-world action RPG using a forward-rendering pipeline, with abundant vegetation, buildings, and translucent effects. The following parameters represent a high-end mobile device at a typical quality setting:
| Parameter | Value | Explanation / basis |
|---|---|---|
| P | 3 | Base rendering, shadows/effects, and post-processing/UI; a conservative estimate of three core passes. |
| G | 12 × 106 bytes | Estimated 300,000 vertices per pass at 40 bytes per vertex, or approximately 12 MB of geometry per pass. |
| R | 2.07 × 106 | Mobile resolution of 1920 × 1080. |
| H | 0.10 | Very low hit rate for a small mobile cache. |
Substituting into the discriminant: Δ ≈ −3.456 × 106, Δ < 0 → TBR is preferred.
Interpretation: the defining mobile characteristics are a very low cache hit rate and a moderate geometry load. Because 1 − H ≈ 0.9, almost all of IMR’s depth and color traffic reaches main memory, making pixel-side bandwidth expensive. TBR, by contrast, pays only 2PG = 72 MB for geometry staging in exchange for zero depth cost and a fixed color cost that is decoupled from overdraw. In this case, TBR has a clear bandwidth advantage. This is also a major reason many mobile GPUs favor tile-based rendering approaches.
Case B: Desktop AAA Game with Deferred Rendering and Complex Post-Processing
This case represents a desktop open-world AAA RPG using a deferred-rendering engine, with many dynamic lights, screen-space reflections, and a rich post-processing chain. The selected parameters assume 4K resolution and the highest quality setting:
| Parameter | Value | Explanation / basis |
|---|---|---|
| P | 25 | Deferred rendering plus an extensive post-processing chain. |
| G | 192 × 106 bytes | Estimated 3 million vertices per pass at 64 bytes per vertex, or approximately 192 MB of geometry per pass. |
| R | 8.29 × 106 | Resolution of 3840 × 2160. |
| H | 0.9 | A large desktop cache provides near-complete coverage. |
Substituting into the discriminant: Δ ≈ 214.55 × 106, Δ > 0 → IMR is preferred.
Interpretation: the high desktop cache hit rate (H = 0.9) reduces IMR’s pixel-side cost to near the theoretical minimum; only 10% of memory accesses reach main memory. At the same time, TBR’s two fixed costs become large. Geometry staging reaches 2PG = 2 × 25 × 192 MB ≈ 10 GB, while pass transitions require approximately 4R × 2(P − 1) ≈ 1.6 GB of bandwidth. In this case, IMR uses less bandwidth than TBR.
Epilogue
A truly first-rate architect does not make a simplistic either-or choice. A first-rate architect can hold two complementary approaches in mind at once and still arrive at an excellent compromise.
IMR places its trust in the pipeline and cache; TBR places its calculation in tiling and on-chip storage. One has zero geometry-bandwidth cost, while the other is nearly immune to pixel bandwidth. Their advantages are complementary.
For selected scenarios, the DCR (Dynamic Cache Rendering) technology proposed for Glenfly’s Arise-series GPUs is designed to capture advantages from both sides: zero depth-bandwidth cost associated with tile-based rendering and zero geometry-bandwidth cost associated with immediate-mode rendering. The approach also avoids an entire wait through the binning stage. The implementation includes many additional details that are outside the scope of this article; readers may consult the relevant patents.
